1. Field of the Invention
The present invention relates to a method for driving a display element and a method for driving a display device.
2. Description of the Related Art
A display element including a current-driven light emitting part and a display device including the display element are known. For example, a display element including an organic electroluminescence (hereinafter, it will be often abbreviated as EL) light emitting part based on the electroluminescence of an organic material (hereinafter, this display element will be often abbreviated simply as the organic EL display element) is attracting attention as a display element capable of high-luminance light emission by low-voltage DC driving.
Similarly to the liquid crystal display device, also for e.g. a display device including the organic EL display element (hereinafter, this display device will be often abbreviated simply as the organic EL display device), the simple-matrix system and the active-matrix system are known as the driving system. The active-matrix system has advantages of being capable of offering high image luminance and so on, although having a defect that the structure is complex. The organic EL display element driven by the active-matrix system includes a light emitting part composed of an organic layer and so on including a light emitting layer and a drive circuit for driving the light emitting part.
As a circuit for driving the organic electroluminescence light emitting part (hereinafter, it will be often referred to simply as the light emitting part), a drive circuit including two transistors and one capacitive part (referred to as the 2Tr/1C drive circuit) is known from e.g. Japanese Patent Laid-open No. 2007-310311. As shown in FIG. 2, this 2Tr/1C drive circuit includes two transistors, a write transistor TRW and a drive transistor TRD, and further includes one capacitive part C1. The other source/drain region of the drive transistor TRD forms a second node ND2, and the gate electrode of the drive transistor TRD forms a first node ND1.
The cathode electrode of a light emitting part ELP is connected to a second power feed line PS2 that is common. A voltage Vcat (e.g. 0 volt) is applied to the second power feed line PS2.
As shown in a timing chart of FIG. 6, pre-processing for executing threshold voltage cancel processing is executed in [period-TP(2)1A]. Specifically, a first node initialization voltage VOfs (e.g. 0 volt) is applied from a data line DTL to the first node ND1 via the write transistor TRW turned to the on-state by a scan signal from a scan line SCL. Thereby, the potential of the first node ND1 becomes VOfs. Furthermore, a second node initialization voltage VCC-L, (e.g. −10 volts) is applied from a power supply unit 100 to the second node ND2 via the drive transistor TRD. Thereby, the potential of the second node ND2 becomes VCC-L. The threshold voltage of the drive transistor TRD is represented as the voltage Vth (e.g. 3 volts). The potential difference between the gate electrode of the drive transistor TRD and the other source/drain region (hereinafter, it will be often referred to as the source region, for convenience) thereof is equal to or larger than Vth, and the drive transistor TRD is in the on-state.
Subsequently, the threshold voltage cancel processing is executed over the period from [period-TP(2)1B] to [period-TP(2)5]. Specifically, the first threshold voltage cancel processing is executed in [period-TP(2)1B]. The second threshold voltage cancel processing is executed in [period-TP(2)3]. The third threshold voltage cancel processing is executed in [period-TP(2)5].
In [period-TP(2)1B], the voltage of the power supply unit 100 is switched from the second node initialization voltage VCC-L, to a drive voltage VCC-H (e.g. 20 volts), with the on-state of the write transistor TRW kept. As a result, the potential of the second node ND2 changes toward the potential obtained by subtracting the threshold voltage Vth of the drive transistor TRD from the potential of the first node ND1. That is, the potential of the second node ND2 rises.
If this [period-TP(2)1B] is sufficiently long, the potential difference between the gate electrode of the drive transistor TRD and the other source/drain region thereof reaches Vth, and the drive transistor TRD enters the off-state. Specifically, the potential of the second node ND2 comes close to (VOfs−Vth) and finally becomes (VOfs−Vth). However, in the example shown in FIG. 6, the length of [period-TP(2)1B] is not enough to sufficiently change the potential of the second node ND2. Therefore, at the end timing of [period-TP(2)1B], the potential of the second node ND2 reaches a certain potential V1 that satisfies the relationship VCC-L<V1<(VOfs−Vth).
At the start timing of [period-TP(2)2], the voltage of the data line DTL is switched from the first node initialization voltage VOfs to a video signal VSig—m−2. In order to prevent the video signal VSig—m−2 from being applied to the first node ND1, the write transistor TRW is turned to the off-state by the signal from the scan line SCL at the start timing of this [period-TP(2)2]. As a result, the first node ND1 becomes the floating state.
Because the drive voltage VCC-H is applied from the power supply unit 100 to one source/drain region of the drive transistor TRD, the potential of the second node ND2 rises from the potential V1 to a certain potential V2. On the other hand, the gate electrode of the drive transistor TRD is in the floating state, and the capacitive part C1 exists. Thus, bootstrap operation occurs at the gate electrode of the drive transistor TRD. Consequently, the potential of the first node ND1 rises in the wake of the potential change of the second node ND2.
At the start timing of [period-TP(2)3], the voltage of the data line DTL is switched from the video signal VSig—m−2 to the first node initialization voltage VOfs. At the start timing of this [period-TP(2)3], the write transistor TRW is turned to the on-state by the signal from the scan line SCL. As a result, the potential of the first node ND1 becomes VOfs. Furthermore, the drive voltage VCC-H is applied from the power supply unit 100 to one source/drain region of the drive transistor TRD. As a result, the potential of the second node ND2 changes toward the potential obtained by subtracting the threshold voltage Vth of the drive transistor TRD from the potential of the first node ND1. That is, the potential of the second node ND2 rises from the potential V2 to a certain potential V3.
At the start timing of [period-TP(2)4], the voltage of the data line DTL is switched from the first node initialization voltage VOfs to a video signal VSig—m−1. In order to prevent the video signal VSig—m−1 from being applied to the first node ND1, the write transistor TRW is turned to the off-state by the signal from the scan line SCL at the start timing of this [period-TP(2)4]. As a result, the first node ND1 becomes the floating state.
Because the drive voltage VCC-H is applied from the power supply unit 100 to one source/drain region of the drive transistor TRD, the potential of the second node ND2 rises from the potential V3 to a certain potential V4. On the other hand, the gate electrode of the drive transistor TRD is in the floating state, and the capacitive part C1 exists. Thus, bootstrap operation occurs at the gate electrode of the drive transistor TRD. Consequently, the potential of the first node ND1 rises in the wake of the potential change of the second node ND2.
As the premise of the operation in [period-TP(2)5], it is necessary that the potential V4 of the second node ND2 be lower than (VOfs−Vth) at the start timing of [period-TP(2)5]. The length from the start timing of [period-TP(2)1B] to the start timing of [period-TP(2)5] is so decided that the condition V4<(VOfs−Vth) is satisfied.
The operation in [period-TP(2)5] is basically the same as the above-described operation in [period-TP(2)3]. At the start timing of this [period-TP(2)5], the voltage of the data line DTL is switched from the video signal VSig—m−1 to the first node initialization voltage VOfs. At the start timing of this [period-TP(2)5], the write transistor TRW is turned to the on-state by the signal from the scan line SCL.
The first node ND1 becomes the state in which the first node initialization voltage VOfs is applied thereto from the data line DTL via the write transistor TRW. Furthermore, the drive voltage VCC-H is applied from the power supply unit 100 to one source/drain region of the drive transistor TRD. Similarly to the above-described operation in [period-TP(2)3], the potential of the second node ND2 changes toward the potential obtained by subtracting the threshold voltage Vth of the drive transistor TRD from the potential of the first node ND1. If the potential difference between the gate electrode of the drive transistor TRD and the other source/drain region thereof reaches Vth, the drive transistor TRD becomes the off-state. In this state, the potential of the second node ND2 is substantially (VOfs−Vth).
Thereafter, in [period-TP(2)6A], the write transistor TRW is set to the off-state. Furthermore, the voltage of the data line DTL is set to the voltage corresponding to the video signal [video signal (drive signal, luminance signal) VSig—m for controlling the luminance of the light emitting part ELP].
Subsequently, write processing is executed in [period-TP(2)6B]. Specifically, the write transistor TRW is turned to the on-state by switching the scan line SCL to the high level. As a result, the potential of the first node ND1 rises toward the video signal VSig—m.
Here, the capacitance of the capacitive part C1 is defined as the value c1, and the value of the capacitance CEL of the light emitting part ELP is defined as the value cEL. Furthermore, the value of the parasitic capacitance between the gate electrode of the drive transistor TRD and the other source/drain region thereof is defined as cgs. If the capacitance between the first node ND1 and the second node ND2 is represented by sign cA, cA=c1+cgs holds. If the capacitance between the second node ND2 and the second power feed line PS2 is represented by sign cB, cB=cEL holds.
When the potential of the gate electrode of the drive transistor TRD changes from VOfs to VSig—m (>VOfs), the voltage between the first node ND1 and the second node ND2 changes. Specifically, the charge based on the change in the potential of the gate electrode of the drive transistor TRD (=the potential of the first node ND1) (VSig—m−VOfs) is distributed depending on the capacitance between the first node ND1 and the second node ND2 and the capacitance between the second node ND2 and the second power feed line PS2. However, the potential change of the second node ND2 is small if the value cB (=cEL) is sufficiently larger than the value cA (=c1+cgs). In general, the value cEL of the capacitance CEL of the light emitting part ELP is larger than the value c1 of the capacitive part C1 and the value cgs of the parasitic capacitance of the drive transistor TRD. For convenience, hereinafter, the description will be made without taking into consideration the potential change of the second node ND2 arising due to the potential change of the first node ND1.
In the above-described operation, the video signal VSig—m is applied to the gate electrode of the drive transistor TRD in the state in which the drive voltage VCC-H is applied from the power supply unit 100 to one source/drain region of the drive transistor TRD.
Therefore, as shown in FIG. 6, the potential of the second node ND2 rises in [period-TP(2)6B]. The amount ΔV of rise of the potential (potential correction value) will be described later. If the potential of the gate electrode of the drive transistor TRD (first node ND1) is defined as Vg and the potential of the other source/drain region thereof (second node ND2) is defined as Vs, the value of Vg and the value of Vs are as follows unless the above-described amount ΔV of rise of the potential of the second node ND2 is not taken into consideration. The potential difference between the first node ND1 and the second node ND2, i.e. the potential difference Vgs between the gate electrode of the drive transistor TRD and the other source/drain region thereof serving as the source region, can be represented by the following Formula (A).Vg=VSig—m Vs≈VOfs−Vth Vgs≈VSig—m−(VOfs−Vth)  (A)
That is, Vgs obtained through the write processing for the drive transistor TRD depends only on the video signal VSig—m for controlling the luminance of the light emitting part ELP, the threshold voltage Vth of the drive transistor TRD, and the voltage VOfs for initializing the potential of the gate electrode of the drive transistor TRD. Furthermore, Vgs has no relation to the threshold voltage Vth-EL of the light emitting part ELP.
Next, a simple description will be made about mobility correction processing. In the above-described operation, in conjunction with the write processing, the mobility correction processing of changing the potential of the other source/drain region of the drive transistor TRD (i.e. the potential of the second node ND2) depending on a characteristic of the drive transistor TRD (e.g. the magnitude of the mobility p) is also executed.
As described above, the video signal VSig—m is applied to the gate electrode of the drive transistor TRD in the state in which the drive voltage VCC-H is applied from the power supply unit 100 to one source/drain region of the drive transistor TRD. As shown in FIG. 6, the potential of the second node ND2 rises in [period-TP(2)6B]. As a result, if the value of the mobility μ of the drive transistor TRD is large, the amount ΔV of rise (potential correction value) of the potential of the source region of the drive transistor TRD is large. If the value of the mobility μ of the drive transistor TRD is small, the amount ΔV of rise (potential correction value) of the potential of the source region of the drive transistor TRD is small. The potential difference Vgs between the gate electrode of the drive transistor TRD and the source region thereof is transformed from that by Formula (A) to that by the following Formula (B).Vgs≈VSig—m−(VOfs−Vth)−ΔV  (B)
Through the above-described operation, the threshold voltage cancel processing, the write processing, and the mobility correction processing are completed. At the start timing of the subsequent [period-TP(2)6C], the first node ND1 is turned to the floating state by switching the write transistor TRW to the off-state by the scan signal from the scan line SCL. The drive voltage VCC-H is applied from the power supply unit 100 to one source/drain region (hereinafter, it will be often referred to as the drain region, for convenience) of the drive transistor TRD. As a result of the above operation, the potential of the second node ND2 rises, and a phenomenon similar to one in a so-called bootstrap circuit occurs at the gate electrode of the drive transistor TRD, so that the potential of the first node ND1 also rises. The potential difference Vgs between the gate electrode of the drive transistor TRD and the source region thereof keeps the value of Formula (B). The current flowing through the light emitting part ELP is a drain current Ids that flows from the drain region of the drive transistor TRD to the source region thereof. If the drive transistor TRD ideally operates in the saturation region, the drain current Ids can be represented by the following Formula (C). The light emitting part ELP emits light with the luminance dependent on the value of the drain current Ids. Details of the coefficient k will be described later.
                                                                        I                ds                            =                              k                ·                μ                ·                                                      (                                                                  V                        gs                                            -                                              V                        th                                                              )                                    2                                                                                                        =                              k                ·                μ                ·                                                      (                                                                  V                        Sig_m                                            -                                              V                        Ofs                                            -                                              Δ                        ⁢                                                                                                  ⁢                        V                                                              )                                    2                                                                                        (        C        )            
According to Formula (C), the drain current Ids is proportional to the mobility μ. For the drive transistor TRD having higher mobility μ, the potential correction value ΔV is larger and the value of (VSig—m−VOfs−ΔV)2 in Formula (C) is smaller. This allows correction of variation in the drain current Ids attributed to variation in the mobility μ of the drive transistor.
The operation of the 2Tr/1C drive circuit, whose outline has been described above, will also be described in detail later.